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INTEGRATED CIRCUITS
DATA SHEET
SAA5290 One page Economy Teletext/TV microcontroller
Preliminary specification File under Integrated Circuits, IC02 February 1995
Philips Semiconductors
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
FEATURES General * Complete one page teletext decoder and TV microcontroller in a single 52-pin package * Eastern European, Western European and Turkish language variants covered in one device * Double size, double width and double height character capability for On-Screen Display (OSD) * Enhanced display features including meshing and shadowing * Separate display and acquisition timing for increased flexibility * Minimum peripheral component count * 525 line and 625 line display synchronization * Standby mode through power-down of teletext and analog hardware. Microcontroller * 16 kbytes masked ROM (16 kbytes EEPROM variant for product development) * 256 bytes of on-chip RAM * Six 6-bit Pulse Width Modulators (PWM) and one 14-bit precision PWM * 4-bit Digital-to-Analog Converter (DAC) and comparator with a 3-input multiplexer allowing implementation of 3 Analog-to-Digital Converters (ADC) in software * 2 high current (10 mA) open-drain outputs * Interrupt logic 0 triggered on rising and falling edges, providing pulse-width measurement for remote control decoding * Master and slave bit-level I2C-bus hardware. ORDERING INFORMATION PACKAGE TYPE NUMBER SAA5290ZP/nnn(1) SAA5290ZP/NVI(2) Notes 1. nnn is a three-digit number referencing the microcontroller program ROM mask. 2. I is a digit number referring to the language variant of the SAA5290ZP/NV. MEMORY NAME ROM EEPROM SDIP52 SDIP52 DESCRIPTION DESCRIPTION
SAA5290
The SAA5290 is a single-chip one page teletext decoder and television control microcontroller. The device will decode 625-line based World System Teletext transmissions and provides television control functions and On-Screen Display (OSD) functions. The teletext decoder hardware is a derivative of the SAA5254 (IVT1.1X), and the TV control functionality provided by an on-chip industrial standard 80C51 microcontroller. A single-page static RAM is included on-board providing a complete one page teletext decoder and OSD memory. The SAA5290 is available as a mask-programmed ROM version. An EEPROM version is also available for product development. Both versions are available in an SDIP52 package.
VERSION SOT247-1 SOT247-1
plastic shrink dual in-line package; 52 leads (600 mil) plastic shrink dual in-line package; 52 leads (600 mil)
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
QUICK REFERENCE DATA SYMBOL VDD IDDM IDDA IDDT fxtal Tamb BLOCK DIAGRAM supply voltage microcontroller supply current analog supply current teletext supply current crystal frequency operating ambient temperature PARAMETER 4.5 - - - - -20 MIN. 5.0 25 35 20 12 - TYP. 40 50 30 - +70
SAA5290
MAX. 5.5 V
UNIT mA mA mA MHz C
handbook, full pagewidth
BLACK 25
IREF 26 TELETEXT ACQUISITION
VDDA 38
V DDT 39
VDDM 44 37 DISPLAY TIMING 36 27 VSYNC HSYNC FRAME
CVBS0 CVBS1
2
23, 24 DATA SLICER
3 ACQUISITION TIMING PAGE RAM DISPLAY
34, 33, 32 35 29
R, G, B VDS COR
SAA5290
OSCIN OSCOUT OSCGND 41 42 40 OSCILLATOR 16K x 8 ROM data RESET 43 80C51 MICROCONTROLLER address 256 x 8 RAM TEXT INTERFACE 31 RGBREF
ANALOG-TODIGITAL CONVERTER
PULSE WIDTH MODULATOR
TIMER/ CTRS/ I 2 C
PORT 3
PORT 2
PORT 1
PORT 0
13 VSSD1
28 VSSD2
22 VSSA
5 9 to 12, 30 P3.0 to P3.4/ ADC0 to ADC2
8 1 to 8 P2.0 to P2.7 PWM
8 45 to 52 P1.0 to P1.7 / INT0, INT1, T0, T1, SDA, SCL
8 14 to 21 P0.0 to P0.7
MLC102
Fig.1 Block diagram.
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
PINNING SYMBOL P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3 P3.4 VSSD1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSSA CVBS0 CVBS1 BLACK IREF FRAME VSSD2 COR RGBREF B G R VDS HSYNC PIN 1 2 3 4 5 6 7 8 9 10 11 12 30 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 analog ground. digital ground 1 for teletext and microcontroller circuits. DESCRIPTION
SAA5290
PORT 2: 8-bit open-drain bidirectional port with alternative functions. P2.0/TPWM is the output for the 14-bit high precision PWM. P2.1/PWM0 to P2.6/PWM5 are the outputs for the 6-bit PWMs 0 to 5.
PORT 3: 5-bit open-drain bidirectional port with alternative functions. P3.0/ADC0 to P3.2/ADC2 are the inputs for the software ADC facility.
PORT 0: 8-bit open-drain bidirectional port. P0.5 and P0.6 have 10 mA current sinking capability at 0.5 V for direct drive of LEDs.
Composite video input. A positive-going 1 V (peak-to-peak) input is required, connected via a 100 nF capacitor. Video black level storage input. This pin should be connected to VSSA via a 100 nF capacitor. Reference current input for analog circuits, connected to VSSA via a 27 k resistor. De-interlace output synchronized with the VSYNC pulse to produce a non-interlaced display by adjustment of the vertical deflection currents. Digital ground 2. Open-drain, active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display. DC input voltage to define the output HIGH level on the RGB pins. Dot rate character output of the BLUE colour information. Dot rate character output of the GREEN colour information. Dot rate character output of the RED colour information. Video/data switch push-pull output for dot rate fast blanking. Horizontal sync dedicated input for a TTL-level version of the horizontal sync pulse. The polarity of this pulse is programmable by register bit TXT1.H POLARITY.
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
SYMBOL VSYNC VDDA VDDT OSCGND OSCIN OSCOUT RESET PIN 37 38 39 40 41 42 43 DESCRIPTION
SAA5290
Vertical sync dedicated input for a TTL-level version of the vertical sync pulse. The polarity of this pulse is programmable by register bit TXT1.V POLARITY. +5 V analog power supply. +5 V teletext power supply. Crystal oscillator ground. 12 MHz crystal oscillator input. 12 MHz crystal oscillator output. If the reset input is HIGH for 2 machine cycles (24 oscillator periods) while the oscillator is running, the SAA5290 is reset. This pin should be connected to VDDM via a 2.2 F capacitor. +5 V microcontroller power supply. PORT 1: 8-bit open-drain bidirectional port with alternative functions. P1.0/INT1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse. P1.1/T0 is the counter/timer 0. P1.2/INT0 is external interrupt 0. P1.3/T1 is the counter/timer 1. P1.6/SCL is the serial clock input for I2C-bus. P1.7/SDA is the serial data port for the I2C-bus.
VDDM P1.0/INT1 P1.1/T0 P1.2/INT0 P1.3/T1 P1.6/SCL P1.7/SDA P1.4 P1.5
44 45 46 47 48 49 50 51 52
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
SAA5290
handbook, halfpage
P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3 VSSD1 P0.0 P0.1
1 2 3 4 5 6 7 8 9 10 11 12 13
52
P1.5
51 P1.4 50 49 48 47 46 45 44 43 42 P1.7/SDA P1.6/SCL P1.3/T1 P1.2/INT0 P1.1/T0 P1.0/INT1 VDDM RESET OSCOUT
41 OSCIN 40 OSCGND
SAA5290
14 15
39 VDDT 38 VDDA 37 VSYNC 36 HSYNC 35 VDS 34 R 33 G 32 B 31 RGBREF 30 P3.4 29 COR 28 VSSD2 27 FRAME
P0.2 16 P0.3 17 P0.4 18 P0.5 P0.6 P0.7 VSSA CVBS0 CVBS1 BLACK IREF 19 20 21 22 23 24 25 26
MLC103
Fig.2 Pin configuration.
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
QUALITY AND RELIABILITY
SAA5290
This device will meet Philips Semiconductors General Quality Specification for Business group "Consumer Integrated Circuits SNW-FQ-611-Part E" (see "Quality Reference Handbook", order number 9398 510 63011). The principal requirements are shown in Tables 1 to 4. Group A Table 1 Acceptance tests per lot TEST Mechanical Electrical Group B Table 2 Processability tests (by package family) TEST Solderability Mechanical Solder heat resistance Group C Table 3 Reliability tests (by process family) TEST Operational life Humidity life CONDITIONS 168 hours at Tj = 150 C temperature, humidity, bias 1000 hours, 85 C, 85% RH (or equivalent test) Tstg(min) to Tstg(max) REQUIREMENTS(1) <1500 FPM; equivalent to <100 FITS at Tj = 70 C <2000 FPM <7% LTPD <15% LTPD <15% LTPD REQUIREMENTS(1) cumulative target: <80 ppm cumulative target: <80 ppm REQUIREMENTS(1)
Temperature cycling performance
<2000 FPM
Table 4 Reliability tests (by device type) TEST ESD and latch-up CONDITIONS ESD Human body model 2000 V, 100 pF, 1.5 k ESD Machine model 200 V, 200 pF, 0 latch-up 100 mA, 1.5 x VDD (absolute maximum) Notes to Tables 1 to 4 1. ppm = fraction of defective devices, in parts per million. LTPD = Lot Tolerance Percent Defective. FPM = fraction of devices failing at test condition, in Failures Per Million. FITS = Failures In Time Standard. REQUIREMENTS(1) <15% LTPD <15% LTPD <15% LTPD
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI VO IO IIOK VSS VDD Tamb Tstg Notes 1. This maximum value has an absolute maximum of 6.5 V independent of VDD. 2. Except in standby mode. CHARACTERISTICS VDD = 5 V 10%; VSS = 0 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDD IDDM IDDA IDDT supply voltage (VDD to VSS) microcontroller supply current analog supply current teletext supply current 4.5 - - - 5.0 25 35 20 5.5 40 50 30 PARAMETER CONDITIONS MIN. TYP. PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) output current (each output) DC input or output diode current difference between VSSD, VSSA and OSCGND difference between VDDM, VDDT and VDDA operating ambient temperature storage temperature note 2 note 1 note 1 CONDITIONS MIN. -0.3 -0.3 -0.3 - - - - -20 -55
SAA5290
MAX. +6.5 V VDD + 0.5 V VDD + 0.5 V 10 20 0.1 0.1 +70 +125
UNIT
mA mA V V C C
MAX.
UNIT
V mA mA mA
Digital inputs RESET VIL VIH ILI CI Vthf Vthr VHYS CI LOW level input voltage HIGH level input voltage input leakage current input capacitance VI = 0 to VDD -0.3 0.7VDD -10 - 0.2VDD - - - - - - - - - 0.33VDD - 0.2VDD - 0.1 V VDD + 0.3 +10 4 - 0.8VDD - 4 V A pF
HSYNC AND VSYNC switching threshold falling switching threshold rising hysteresis voltage input capacitance V V V pF
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
SYMBOL Digital outputs R, G AND B (note 1) VOL VOH |ZO| CL IO tr tf LOW level output voltage HIGH level output voltage output impedance load capacitance DC output current output rise time output fall time IOL = 2 mA IOH = -2 mA 0 VRGBREF - 0.3 - - - between 10% and 90%; - CL = 50 pF between 90% and 10%; - CL = 50 pF - IOL = 2 mA 0 - - IOL = 1.6 mA IOH = -1.6 mA 0 VDD - 0.3 - between 10% and 90%; - CL = 50 pF between 90% and 10%; - CL = 50 pF - - VRGBREF - - - - - 0.2 PARAMETER CONDITIONS MIN. TYP.
SAA5290
MAX.
UNIT
V V pF mA ns ns
VRGBREF + 0.4 150 50 -4 20 20
COR (OPEN-DRAIN OUTPUT) VOH VOL IOL CL VDS VOL VOH CL tr tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time - - - - - 0.2 VDD + 0.4 50 20 20 V V pF ns ns HIGH level pull-up output voltage LOW level output voltage LOW level output current load capacitance - - - - VDD 0.5 2 25 V V mA pF
R, G, B AND VDS tskew FRAME VOH VOL IOL CL HIGH level output voltage LOW level output voltage LOW level output current load capacitance IOL = 8 mA IOL = -8 mA 0 VDD - 0.5 -8 - - - - - 0.5 VDD +8 100 V V mA pF skew delay between any two pins - 20 ns
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA5290
MAX.
UNIT
Digital input/outputs P0.0 TO P0.4, P0.7, P1.0 TO P1.5, P2.0 TO P2.7 AND P3.0 TO P3.5 VIL VIH CI VOL CL VIL VIH CI VOL CL VIL VIH CI VOL CL tf LOW level input voltage HIGH level input voltage input capacitance LOW level output voltage load capacitance IOL = 3.2 mA -0.3 - 0 - -0.3 - IOL = 10 mA 0 - -0.3 3.0 - IOL = 3 mA between 3 and 1 V 0 - - - - - - - - - - - - - - - - 0.2VDD - 0.1 V VDD + 0.3 4 0.45 50 V pF V pF 0.2VDD + 0.9 -
P0.5 AND P0.6 LOW level input voltage HIGH level input voltage input capacitance LOW level output voltage load capacitance 0.2VDD - 0.1 V VDD + 0.3 4 0.45 50 V pF V pF 0.2VDD + 0.9 -
P1.6 AND P1.7 LOW level input voltage HIGH level input voltage input capacitance LOW level output voltage load capacitance output fall time +1.5 VDD + 0.3 5 0.5 400 200 V V pF V pF ns
Analog inputs CVBS0 AND CVBS1 Vsync Vvid(p-p) Zsource VIH |ZI| CI IREF Rgnd VI II resistor to ground - -0.3 - 27 - - - VDD 12 k sync voltage amplitude video input voltage amplitude (peak-to-peak value) source impedance HIGH level input voltage input impedance input capacitance 0.1 0.7 - 3.0 2.5 - 0.3 1.0 - - 5.0 - 0.6 1.4 250 VDD + 0.3 - 10 V V V k pF
RGBREF (note 1) input voltage DC input current V mA
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
SYMBOL PARAMETER CONDITIONS MIN. -0.3 - TYP.
SAA5290
MAX.
UNIT
ADC0, ADC1 AND ADC2 VIL LOW level input voltage VDD V
Analog input/output BLACK Cblack Vblack ILI storage capacitor to ground black level voltage for nominal sync amplitude input leakage current - 1.8 -10 100 2.15 - - 2.5 +10 nF V A
Crystal oscillator OSCIN VIL VIH CI OSCOUT fosc CO fxtal CL C1 C0 Rr Txtal Xj Xd Notes 1. All RGB current is sourced from the RGBREF pin. The maximum effective series resistance between RGBREF and the R, G and B pins is 150 . 2. Crystal order number 4322 143 05561. crystal oscillator frequency output capacitance - - - - Tamb = 25 C Tamb = 25 C Tamb = 25 C Tamb = 25 C - - - -20 - - 12 - 12 32 18.5 4.9 35 +25 - - - 10 - - - - - +70 50 x 10-6 30 x 10-6 MHz pF LOW level input voltage HIGH level input voltage input capacitance -0.3 0.7VDD - - - - 0.2VDD - 0.1 V VDD + 0.3 10 V pF
CRYSTAL SPECIFICATION (note 2) nominal frequency load capacitance series capacitance parallel capacitance resonance resistance temperature range adjustment tolerance drift MHz pF fF pF C
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
Table 5 Characteristics for the I2C-bus interface SYMBOL SCL timing tHD;STA tLOW tHIGH trC tfC tSU;DAT1 tHD;DAT tSU;STA tSU;STO tBUF trD tfD Notes 1. This parameter is determined by the user software. It must comply with the I2C-bus specification. START condition hold time SCL LOW time SCL HIGH time SCL rise time SCL fall time 4.0 s 4.7 s 4.0 s 1.0 s 0.3 s 250 ns 0 ns 4.7 s 4.0 s 4.7 s 1.0 s 0.3 s note 1 note 1 4.0 s; note 2 note 3 0.3 s; note 4 PARAMETER INPUT OUTPUT
SAA5290
I2C-BUS SPECIFICATION 4.0 s 4.7 s 4.0 s 1.0 s 0.3 s 250 ns 0 ns 4.7 s 4.0 s 4.7 s 1.0 s 0.3 s
SDA timing data set-up time data hold time repeated START set-up time STOP condition set-up time bus free time SDA rise time SDA fall time note 1 note 1 note 1 note 1 note 1 note 3 0.3 s; note 4
2. This value gives the auto-clock pulse length which meets the I2C-bus specification for the special crystal frequency. Alternatively, the SCL pulse must be timed by software. 3. The rise time is determined by the external bus line capacitance and pull-up resistor. It must be less than 1 s. 4. The maximum capacitance on bus lines SDA and SCL is 400 pF.
repeated START condition START or repeated START condition STOP condition t rD t SU;STA START condition
SDA (input / output) t BUF t SU;STO 0.7VDD 0.3VDD t SU;DAT3 t SU;DAT2
0.7V DD 0.3VDD t fD t rC t fC
SCL (input / output)
t HD;STA
t LOW
t HIGH
t SU;DAT1
t HD;DAT
MLC104
Fig.3 I2C-bus interface timing.
dth
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
FUNCTIONAL DESCRIPTION Introduction The SAA5290 is an integrated teletext decoder and microcontroller. The teletext decoder is derived from the SAA5254 single page teletext decoder IC, with a number of enhancements to increase its suitability for on-screen display applications. The microcontroller is a derivative of the industry standard 80C51 microcontroller. A block diagram of the SAA5290 is given in Fig.1. Microcontroller The functionality of the microcontroller used on the SAA5290 is described here with reference to the industry standard 80C51 microcontroller. A full description of its functionality can be found in the handbook 80C51-based 8-bit microcontrollers IC20. Using the 80C51 as a reference, the changes made for the SAA5290 fall into two categories, features not supported by the SAA5290 and features found on the SAA5290 but not supported by the 80C51. 80C51 features not supported by the SAA5290 INTERRUPT PRIORITY The IP SFR is not implemented and all interrupts are treated with the same priority level. The SAA5290 retains the normal prioritization of interrupts within a level. Table 6 Interrupts and their vector addresses PROGRAM MEMORY ADDRESS 000H 003H 00BH 013H 01BH 053H OFF-CHIP MEMORY
SAA5290
The SAA5290 does not support the use of off-chip program memory or off-chip data memory. This means that the SAA5290 does not have any of EA, RD, WR, ALE or PSEN pins. The 4 MOVX instructions which move data to and from external RAM should not be used. IDLE AND POWER-DOWN MODES Idle and power-down modes are not supported by the SAA5290. As a consequence, the respective bits in PCON are not available. UART FUNCTION The 80C51 UART is not available in the SAA5290. As a consequence the SCON and SBUF SFRs are removed and the ES bit in the IE SFR is unavailable. Additional features for the SAA5290 The following features are provided by the SAA5290 in addition to the standard 80C51 features. INTERRUPTS The external INT1 interrupt is modified to generate an interrupt on both the rising and falling edges of the INT1 pin, when EX1 bit is set. This facility allows for software pulse width measurement for handling of a remote control. BIT LEVEL I2C-BUS INTERFACE The bit-level serial I/O supports the I2C-bus. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C-bus specification concerning the input levels and output drive capability. Consequently, these pins have an open-drain output configuration. All the four following modes of the I2C-bus are supported. * Master transmitter * Master receiver * Slave transmitter
EVENT Reset External INT0 Timer 0 External INT1 Timer 1 I2C-bus
February 1995
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Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
* Slave receiver. hardware, The advantages of the bit-level compared with a full software I2C-bus implementation are: * The hardware can generate the SCL pulse * Testing a single bit (RBF or WBF respectively) is sufficient as a check for error-free transmission. hardware operates on serial bit level The bit-level and performs the following functions: * Filtering the incoming serial data and clock signals * Recognizing the START condition * Generating a serial interrupt request SI after reception of a START condition and the first falling edge of the serial clock * Recognizing the STOP condition * Recognizing a serial clock pulse on the SCL line * Latching a serial bit on the SDA line (SDI) * Stretching the SCL LOW period of the serial clock to suspend the transfer of the next serial data bit * Setting Read Bit Finished (RBF) when the SCL clock pulse has finished and Write Bit Finished (WBF) if there is no arbitration loss detected (i.e. SDA = logic 0 while SDO = logic 1) * Setting a serial clock LOW-to-HIGH detected (CLH) flag * Setting a Bus Busy (BB) flag on a START condition and clearing this flag on a STOP condition * Releasing the SCL line and clearing the CLH, RBF and WBF flags to resume transfer to the next serial data bit * Generating an automatic clock if the single bit data register S1BIT is used in master mode. The following functions must be done in software: * Handling the I2C-bus START interrupts * Converting serial data to parallel data when receiving * Converting parallel data to serial data when transmitting * Comparing the received slave address with its own address * Interpreting the acknowledge information * Guarding the I2C-bus status if RBF or WBF = logic 0. Additionally, if acting as master: * Generating START and STOP conditions * Handling bus arbitration * Generating serial clock pulses if S1BIT is not used. Three SFRs support the function of the bit-level I2C-bus hardware, they are S1INT, S1BIT and S1SCS. February 1995 14 I2C-bus I2C-bus LED SUPPORT
SAA5290
Port pins P0.5 and P0.6 have a 10 mA current sinking capability to enable LEDs to be driven directly. PWM DACS The SAA5290 has six 6-bit PWM DACs and one14-bit PWM DAC. These allow direct control of other parts of the television. The low resolution 6 bit DACs are controlled by their corresponding SFR (PWM0 to PWM5) and are connected as alternative outputs of Port P2. The port bit corresponding to the PWM should be set to logic 1 for correct operation of the PWM. Table 7 Special Function Registers PWM0 to PWM5 D7 PWE D6 - D5 PV5 D4 PV4 D3 PV3 D2 PV2 D1 PV1 D0 PV0
If the PWE bit for a particular port is set to logic 1, the PWM is active and controls its assigned port pin. If the PWE bit is set to logic 0 the corresponding port pin is controlled by the bit in the corresponding port register for that port. The output of the PWM is a pulse of period 21.33 s with a duty cycle determined by the binary value, PV5 to PV0, multiplied by 0.33 s. The 14 bit PWM is controlled with SFR registers TDACL and TDACH. Table 8 Special Function Register TDACL D7 TD7 D6 TD6 D5 TD5 D4 TD4 D3 TD3 D2 TD2 D1 TD1 D0 TD0
Table 9 Special Function Register TDACH D7 PWE D6 - D5 D4 D3 D2 D1 D0 TD8
TD13 TD12 TD11 TD10 TD9
If the PWE bit is set to logic 1, the TPWM is active and controls Port P2.0. If the PWE bit is set to logic 0 the port pin is controlled by the bit in the corresponding port register for P2.0. The output of the TPWM is a pulse of period 42.66 s with a duty cycle determined by the binary value, TD13 to TD7, multiplied by 0.33 s.
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
The 7 least significant bits, TD6 to TD0, extend the HIGH time of a proportion of the pulses by 0.33 s. If the LSB is set then 1 in 128 cycles is extended, if bit 1 is set then 1 in 64 cycles is extended, and so on. SOFTWARE ADC Up to 3 successive approximation ADCs can be implemented in software by making use of the on-board 4-bit DAC and multiplexed voltage comparator. The software ADC uses 3 analog inputs which are multiplexed with P3.0 to P3.2. The control of the ADC is achieved using the SAD SFR. SAD.5 and SAD.6 select one of the three inputs to pass to the comparator. The other input comes from the DAC whose input is set by SAD bits 0 to 3. The output of the comparator is SAD bit 7 and is valid by the next instruction after starting the comparison by setting SAD.ST to logic 1. Microcontroller interfacing The 80C51 CPU communicates with the peripheral functions using Special Function Registers (SFRs) which are addressed as RAM locations. The registers in the teletext decoder appear as normal SFRs in the microcontroller memory map, but are written to using a serial bus. This bus is controlled by dedicated hardware which uses a simple handshake system for software synchronization. The SFR memory map is given in Table 10.
SAA5290
February 1995
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Table 10 SAA5290 Special Function Register map (note 1) BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION MSB E7 F7 F6 F5 F4 F3 F2 F1 F0 00H E6 E5 E4 E3 E2 E1 E0 00H LSB RESET VALUE (HEX)
February 1995 - 00H 00H X0H FFH FFH A0 B0 D0 PV1 PV1 PV2 PV2 PV3 PV4 PV3 PV2 PV2 PV1 PV1 PV1 PV1 P PV0 PV0 PV0 PV0 PV0 PV0 - - PV2 - - PV3 - PV4 - 00H FFH XXX11111B XXXX00XXB 000000X0B - AF EA 87 97 A7 - B4 GF1 D3 RS0 PV3 PV3 PV3 PV2 0V D2 D1 GF0 D4 RS1 PV4 PV4 PV4 PV4 B3 B2 B1 D7 CY PWE PWE PWE PWE PWE PWE SDI/ SDO PV5 PV5 PV5 PV5 PV5 PV5 AC F0 D6 D5 - - A6 A5 A4 A3 A2 A1 96 95 94 93 92 91 90 86 85 84 83 82 81 80 ES1 ET1 EX1 ET0 EX0 AE AD AC AB AA A9 A8 - - - - - - - - - - - - - -
SYMBOL
DESCR.
DIRECT ADDR. (HEX)
ACC(2)
Accumulator
E0H
B(2)
B register
F0H
Philips Semiconductors
DPTR:
Data Pointer (2 bytes):
DPH
High byte
83H
DPL
Low byte
82H
IE(2)(3)
Interrupt Enable
A8H
P0(2)
Port 0
80H
One page Economy Teletext/TV microcontroller
P1(2)
Port 1
90H
P2(2)
Port 2
A0H
P3(2)(3)
Port 3
B0H
PCON(3)
87H
16
Power Control
PSW(2)
Program Status Word
D0H
PWM0(3)
Pulse Width Modulator 0
D5H
PWM1(3)
Pulse Width Modulator 1
D6H
PWM2(3)
Pulse Width Modulator 2
D7H
PWM3(3)
Pulse Width Modulator 3
DCH
PWM4(3)
Pulse Width Modulator 4
DDH
PWM5(3)
Pulse Width Modulator 5
DEH
Preliminary specification
SAA5290
S1BIT(3)
Serial I2C data
D9H
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION MSB SI DF SDI/ SDO EF VHI 8F TF1 PWE TD7 - - - - GATE X24 POS AUTO FRAME C/T M1 M0 GATE - - - - - C/T DISABLE FRAME - - - - - - - - - - - - - M1 - - - - - - TD6 TD5 TD4 TD3 TD2 TD1 TD13 TD12 TD11 TD10 TD9 TD8 TD0 - - - - M0 TR1 TF0 TR0 IE1 IT1 IE0 IT0 8E 8D 8C 8B 8A 89 88 CH1 CH0 ST SAD3 SAD2 SAD1 SAD0 07H 00H 00H 00H 00H 00H 00H 00H 00H 00H EE ED EC EB EA E9 E8 00H SCI/ SDO CLH BB RBF WBF STR ENS DE DD DC DB DA D9 D8 - - LSB
SYMBOL
DESCR.
DIRECT ADDR. (HEX)
RESET VALUE (HEX)
February 1995
S1INT(3)
Serial I2C interrupt
DAH
Philips Semiconductors
S1SCS(2)(3) Serial I2C control
D8H
SAD(2) (3)
Software A to D
E8H
SP
Stack Pointer 81H
TCON(2)
Timer/counter 88H control
One page Economy Teletext/TV microcontroller
TDACH
TPWM High byte
D3H
TDACL
TPWM Low byte
D2H
TH0
Timer 0 High byte
8CH
17 DISABLE DISPLAY HDR STATUS ROLL ROW ONLY X26 PRD4 FULL FIELD PRD3 8-BIT ACQ OFF SC2 PRD2
TH1
Timer 1 High byte
8DH
TL0
Timer 0 Low byte
8AH
TL1
Timer 1 Low byte
8BH
TMOD
Timer/counter 89H mode
TXT0(3)
Teletext register 0
C0H
TXT1(3)
Teletext register 1
C1H
FIELD H V 00H POLARITY POLARITY POLARITY SC1 PRD1 SC0 PRD0 00H 00H
TXT2(3)
Teletext register 2
C2H
SAA5290
Preliminary specification
TXT3(3)
Teletext register 3
C3H
BIT ADDRESS, SYMBOL OR ALTERNATIVE PORT FUNCTION MSB EAST/ WEST COR OUT COR OUT SNG/DBL BOX ON HEIGHT 24 CVBS0/ CVBS1 R0 C0 D0 TXT ON B9 VIDEO QUALITY B8 TXT I/FACE BUSY 00H R3 C3 D3 ROM VER R1 BB BA ROM VER R0 D2 D1 C2 C1 R2 R1 BOX ON 1-23 BOX ON 0 00H COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN 00000011B COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN 00000011B B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE 00H BKGND OUT BKGND OUT STATUS CURSOR CONCEAL TOP/ ROW ON /REVEAL BTM TOP CLEAR MEM. C5 D5 ROM VER R3 BD BC ROM VER R2 D4 C4 D6 ROM VER R4 BE A0 R4 D7 625/525 SYNC BF BKGND IN BKGND IN LSB
SYMBOL
DESCR.
DIRECT ADDR. (HEX)
RESET VALUE (HEX)
February 1995 00H 00H 00H 00H
TXT4(3)
Teletext register 4
C4H
Philips Semiconductors
TXT5(3)
Teletext register 5
C5H
TXT6(3)
Teletext register 6
C6H
TXT7(3)
Teletext register 7
C7H
TXT8(3)
Teletext register 8
C8H
One page Economy Teletext/TV microcontroller
TXT9(3)
Teletext register 9
C9H
TXT10(3)
Teletext register 10
CAH
TXT11(3)
18
Teletext register 11
CBH
TXT12(3)
Teletext register 12
CCH
TXT13(2)(3)
Teletext register 13
B8H
Notes
1. The star () indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. SFRs are bit addressable.
3. SFRs are modified or added to the 80C51 SFRs.
Preliminary specification
SAA5290
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
Table 11 SFR description REGISTER IE - Interrupt Enable EA ES1 ET1 EX1 ET0 EX0 Disable all interrupts (logic 0) or use individual enable bits (logic 1). I2C-bus interrupt enable (logic 1). Enable Timer 1 overflow interrupt (logic 1). Enable external interrupt 1 (logic 1). Enable Timer 0 overflow interrupt (logic 1). Enable external interrupt 0 (logic 1). FUNCTION
SAA5290
PCON - Power Control GF0 GF1 General purpose flag bit 0. General purpose flag bit 1.
PWM0 to PWM5 - 6-bit Pulse Width Modulator control registers PWE PV0 to PV5 Activate this 6-bit PWM and take over port pin (logic 1). Value to output by this 6-bit PWM.
SAD - Software ADC control VHI CH0 and CH1 ST SAD0 to SAD3 Analog input voltage greater than DAC output voltage (logic 1). See Table 12. Initiate voltage comparison (logic 1). This is automatically reset. 4-bit DAC input value. The DAC output of this value is compared with analog input voltage.
S1BIT - Serial I2C-bus data (READ) SDI I2C-bus data bit latched-in from SDA on the last rising edge of SCL.
S1BIT - Serial I2C-bus data (WRITE) SDO I2C-bus data bit output.
S1INT - Serial I2C-bus interrupt SI I2C-bus interrupt flag.
S1SCS - Serial I2C-bus control (READ) SDI SCI CLH BB RBF WBF STR ENS Serial data input at SDA. Serial clock input at SCL. Clock LOW-to-HIGH transition flag. Bus busy flag. Read bit finished flag. Write bit finished flag. Clock stretching enable (logic 1). Enable serial I/O (logic 1).
February 1995
19
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
REGISTER S1SCS - Serial I2C-bus control (WRITE) SDO SCO CLH STR ENS Serial data output at SDA. Serial clock output at SCL. Clock LOW-to-HIGH transition. Clock stretching enable (logic 1). Enable serial I/O (logic 1). FUNCTION
SAA5290
TDACH - 14-bit PWM MSB register PWE TD8 to TD13 Activate this 14-bit PWM and take over port pin (logic 1). 6 LSBs of this value to be output by the 14-bit PWM.
TDACL - 14-bit PWM LSB register TD0 to TD7 8 LSBs of this value to be output by the 14-bit PWM.
TXT0 - Teletext register 0 (WRITE only) X24 POSITION AUTO FRAME Store packet 24 in extension packet memory (logic 0) or page memory (logic 1). Frame output switched off automatically if any video displayed (logic 1).
DISABLE HDR ROLL Do not write rolling headers and time into memory (logic 1). STATUS ROW ONLY Display only memory row (logic 1). DISABLE FRAME Frame output always LOW (logic 1). TXT1 - Teletext register 1 (WRITE only) 8-BIT ACQ OFF X26 FULL FIELD FIELD POLARITY H POLARITY V POLARITY Data in packets 0 to 24 written into memory without error checking (logic 1). Prevent teletext acquisition section writing to memory (logic 1). Disable automatic processing of packet 26 data (logic 1). Accept teletext on TV lines 2 to 22 only (logic 0) or on any line (logic 1). VSYNC in first half of the line (logic 0) or second half of the line (logic 1) at start of even field. HSYNC input positive-going (logic 0) or negative-going (logic 1). VSYNC input positive-going (logic 0) or negative-going (logic 1).
TXT2 - Teletext register 2 (WRITE only) SC0 to SC2 Start column at which page request data written into TXT3 SFR is placed.
TXT3 - Teletext register 3 (WRITE only) PRD0 to PRD4 Page request data.
TXT4 - Teletext register 4 (WRITE only) B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE EAST/WEST Enable meshing of area with black background (logic 1). Enable meshing of area with other background colours (logic 1). Black background colour is transparent i.e. video is displayed (logic 1). Enable south-east shadowing (logic 1). Western European languages displayed (logic 0) or Eastern European languages displayed (logic 1).
February 1995
20
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
REGISTER TXT5 - Teletext register 5 (WRITE only) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN Background colour displayed outside teletext boxes (logic 1). Background colour displayed inside teletext boxes (logic 1). COR output active outside teletext boxes (logic 1). COR output active inside teletext boxes (logic 1). Text displayed outside teletext boxes (logic 1). Text displayed inside teletext boxes (logic 1). Video picture displayed outside teletext boxes (logic 1). Video picture displayed inside teletext boxes (logic 1). FUNCTION
SAA5290
TXT6 - Teletext register 6 (WRITE only) - This register has the same meaning as TXT5 but is only invoked if either newsflash (C5) or the subtitle (C6) bit in Row 25 of the basic page memory is set.
TXT7 - Teletext register 7 (WRITE only) STATUS ROW TOP CURSOR ON CONCEAL/REVEAL TOP/BOTTOM SNG/DBL HEIGHT BOX ON 24 BOX ON 1-23 BOX ON 0 Display Row 24 below (logic 0) or above (logic 1) teletext page. Display cursor at location pointed to by TXT9 and TXT10 (logic 1). Display characters in areas with the conceal attribute set (logic 1). Display Rows 0 to 11 (logic 0) or 12 to 23 (logic 1) when the double height bit is set. Display each character at twice normal height (logic 1). Enable teletext boxes in memory Row 24 (logic 1). Enable teletext boxes in memory Rows 1 to 23 (logic 1). Enable teletext boxes in memory Row 0 (logic 1).
TXT8 - Teletext register 8 (WRITE only) CVBS0/CVBS1 CVBS0 input (logic 0) or CVBS1 (logic 1) inputs used for teletext.
TXT9 - Teletext register 9 (WRITE only) CLEAR MEMORY A0 R0 to R4 Write 20H into every location in teletext memory (logic 1). Access basic page memory (logic 0) or extension packet memory (logic 1) with TXT11 SFR. Memory row to be accessed with TXT11 SFR.
TXT10 - Teletext register 10 (WRITE only) C0 to C5 Memory column to be accessed with TXT11 SFR.
TXT11 - Teletext register 11 D0 to D7 data byte written to, or read from, teletext memory.
February 1995
21
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
REGISTER TXT12 - Teletext register 12 (READ only) 625/525 SYNC ROM VER R0 to R4 TXT ON VIDEO QUALITY FUNCTION
SAA5290
A 625 line CVBS signal (logic 0), or a 525 line CVBS signal (logic 1) is being input. Mask programmable to identify character set version. Teletext power has been applied to the device (logic 1). CVBS input can be locked on by the teletext decoder (logic 1).
TXT13 - Teletext register 13 (READ only) TXT I/FACE BUSY Text interface busy and no access for either READ or WRITE is allowed to SFRs TXT0 to TXT11 (logic 1). This register bit performs the software handshake to the teletext control registers.
Table 12 CH1 and CH0 selection CH1 0 0 1 1 CH0 0 1 0 1 INPUT PIN none ADC0 ADC1 ADC2
February 1995
22
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
TELETEXT DECODER FUNCTIONAL DESCRIPTION Data slicer The data slicer extracts the digital teletext data from the incoming analog waveform. This is performed by sampling the CVBS waveform and processing the samples to extract the teletext data and clock. Acquisition timing The acquisition timing is generated from a logic level positive-going composite sync signal `VCS'. This signal is generated by the sync separator circuit which adaptively slices the sync pulses at 50% of their height. It is able to do this over a wide range of sync amplitudes by using the same basic principle used on VIP1 (SAA5230) and VIP2 (SAA5231). Figure 4 is a block diagram showing the principles of operation. It relies upon the fact that the ratio of the sync width to the line time is approximately 13 : 1. In order to slice the sync pulse at the correct 50% level two currents are generated.
SAA5290
One is constant and is proportional to the difference between the black level of the video and the slicing level. The other is produced only when the video is below the slicing level, and is also proportional to the difference between the slicing level and the input, but has a magnitude13 times greater. The black level is determined by a sync-gated peak detector. The video is negatively peak detected into an external capacitor (BLACK, pin 25), but not during the sync pulse VCS. The two currents are integrated on the CVBS input coupling capacitor and the net effect is to alter the mean input voltage until the (fixed) slicing level is correct. The acquisition clocking and timing are locked to the VCS signal using a digital phased-locked-loop. The phase error in the acquisition phase-locked-loop is detected by a signal quality circuit which disables acquisition if poor signal quality is detected.
handbook, full pagewidth
VDD Vref 1/3Vi (mA)
CVBS VCS FILTER Vref (= slicing level)
FILTER gated negative peak detector
1/39V i(mA) Vref
BLACK
MLC105
Fig.4 Sync separator block diagram.
February 1995
23
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
Teletext acquisition The SAA5290 is able to acquire 625-line World System Teletext. Teletext is acquired under control of the on-board 80C51 microcontroller. Pages are requested by writing a series of bytes into the TXT3 SFR which corresponds to the number of the page required. The bytes written into TXT3 are put into a small RAM with an auto-incrementing address. The start address for the RAM is set using the SFR TXT2 register. Table 13 shows the contents of the page request RAM. Table 13 Register map for page requests (TXT3); note 1 START COLUMN 0 1 2 3 4 5 6 PRD4 DO CARE Magazine DO CARE Page tens DO CARE Page units DO CARE Hours tens DO CARE Hours units DO CARE Minutes tens DO CARE Minutes units Note 1. X = don't care. Page memory organization The acquired teletext packets each contain 40 bytes of data and one packet is stored in each row of the text memory. The page memory organization is given in Fig.5. Rows 0 to 23 form the teletext page; Row 24 is available for status messages and FLOF/FASTEXT prompt information. MU3 MU2 MU1 X MT2 MT1 HU3 HU2 HU1 X X HT1 PU3 PU2 PU1 PT3 PT2 PT1 HOLD MAG2 MAG1 PRD3 PRD2 PRD1
SAA5290
If the `DO CARE' bit for part of the page number is set to logic 0 then that part of the page number is ignored when the acquisition section is deciding whether a page being received off air should be stored or not. For example if the `DO CARE' bits for the 4 subcode digits are all set to logic 0 then every subcode version of the page will be captured. When the `HOLD' bit is set to logic 0 the acquisition section will not recognize any page as having the correct page number and no pages will be captured.
PRD0
MAG0 PT0 PU0 HT0 HU0 MT0 MU0
February 1995
24
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
SAA5290
handbook, full pagewidth
7 characters for status 1 678
fixed character written by hardware, alphanumerics white normally, alphanumerics green when looking for display page
8 characters usually rolling (time) 31 32 39
ROW 0 1 2 3 4
24 characters from page header rolling when display page looked for
MAIN PAGE DISPLAY AREA
5 to 20
PACKET X / 22 PACKET X / 23 PACKET X24 STORED HERE IF TXT0.7 = 1 10 14 10 bytes for received page information 14 bytes free for use by microcontroller
MLC106
21 22 23 24 25
Fig.5 Basic page memory organization.
ROW 0 (see Fig.5) Row 0 is for the page header. The first seven characters (0 to 6) are free for status messages. Character 8 is an alphanumeric white or green control character, written automatically by SAA5290 to give a green rolling header when a page is being looked for. The last eight characters are for rolling time. ROW 25 (see Fig.5) The first 10 bytes of row 25 contain control data relating to the received page as shown in Table 14. The remaining 14 bytes are free for use by the microcontroller. Extension packet memory organization If TXT0.X24 POS bit is set to logic 0, then Packet 24 is written into Row 0 of the extension memory. Packet X27/0 is written to Row 1 of the extension memory, with bytes 0 to 37 being Hamming checked automatically. Packet 8/30 is written to Row 2 of the extension memory, with bytes 0 to 6 being 8/4 Hamming checked, bytes 7 to 19 unchecked and bytes 20 to 39 odd parity checked.
Packet 26 processing The SAA5290 contains on-board hardware processing of Packet 26 data. If a character corresponding to that being transmitted is available in the character set then the correct character code is written into the display memory.
handbook, halfpage
ROW 0 1 2
MLC107
PACKET X24 if TXT0.X24 POS = 0 PACKET X27 / 0 PACKETS 8 / 30 / 0 to 15
Fig.6 Organization of the extension memory.
February 1995
25
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
Table 14 Row 25 received control data format ROW 25 D0 D1 D2 D3 D4 D5 D6 D7 Column PU0 PU1 PU2 PU3 0 0 0 0 PT0 PT1 PT2 PT3 0 0 0 1 MU0 MU1 MU2 MU3 0 0 0 2 MT0 MT1 MT2 C4 0 0 0 3 HU0 HU1 HU2 HU3 0 0 0 4 HT0 HT1 C5 C6 0 0 0 5 C7 C8 C9 C10 0 0 0 6 C11 C12 C13 C14 0 0 0 7
SAA5290
MAG0 MAG1 MAG2 0 0 0 0 8
0 0 0 0 0 PBLF 0 0 9
HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND
Table 15 Page number and sub-code for Table 14 BIT NAME Page number MAG PU PT PBLF HAM.ER Page sub-code MU MT HU HT C4 to C14 minutes units minutes tens hours units hours tens transmitted control bits magazine page units page tens page being looked for Hamming error in corresponding byte DESCRIPTION
February 1995
26
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
Display The capabilities of the display are based on the requirements of level 1 teletext, with some enhancements for use with locally generated On-Screen Displays (OSD). The display consists of 25 rows each of 40 characters, with the characters displayed being those from Rows 0 to 24 of the basic page memory. The page memory stores 8-bit character codes which correspond to 260 displayable characters and 44 control codes, normally displayed as spaces. Each character is defined by a matrix 12 pixels high and 10 pixels deep. When displayed each pixel is 0.5 s wide and 1 TV line, in each field, high. The SAA5290 signals the TV display circuits to display the RGB outputs of the SAA5290 rather than video picture by setting VDS HIGH. The way in which this signal is switched is controlled by the TXT5 and TXT6 SFRs. There are three control functions: background on, text on and picture on. There are separate bits for each function for inside and outside teletext boxes and if the newsflash or subtitle bits are set. This allows the software to configure the type of display required. The effect of the combination of these bits is given in Table 16. The COR bits in Register 5 and Register 6 control when the output is pulled LOW. This output is intended to act on the TV display circuits to reduce the contrast of the video display. Table 16 Display mode PICTURE ON 0 0 0 1 1 1 TEXT ON 0 1 1 0 1 1 BACKGROUND ON X 0 1 X 0 1 text mode, black screen text mode, background always black text mode TV mode mixed mode and TV mode text mode, TV picture outside text area RESULT
SAA5290
The display character set is given in Fig.9. The character set provided contains all the characters required to display Eastern and Western European languages. Register bit TXT4.EAST/ WEST sets whether Eastern or Western languages are set with the C12 to C14 bits. In order to make on-screen displays easy to use, the SAA5290 contains additional display attributes in Column 11. Control codes are categorized as `set at' or `set after'. `Set at' means the code has effect at the current character position and `set after' means they have effect from the following character. Codes 11/0 to 11/7 are always `set at'. Codes 11/11 to 11/15 are `set after' when defining the start of an OSD box and `set at' when ending an OSD box. Codes 11/12 to 11/15 force a box condition allowing on-screen display messages to be displayed without having to erase the whole contents of the teletext page. On-screen displays are only available in TV mode and not in text mode. In mixed text and TV mode the displayed screen is not defined if an OSD box is encountered in the page memory.
Display timing The display circuitry is driven from the H/VSYNC inputs, and is independent of the input video signal. Consequently HSYNC and VSYNC are always required to slave synchronize the display. The FRAME output of the SAA5290 is provided to facilitate de-interlacing the teletext display. The behaviour of FRAME is controlled via the register bits TXT0.DISABLE FRAME, TXT0.AUTO FRAME and TXT1.FIELD POLARITY. If the active edge of VSYNC occurs in the first half of a TV line then the field is even, and if the active edge of VSYNC is in the second half of a line then the field is odd. The active edge is controlled with TXT1.V POLARITY. With TXT0.AUTO FRAME LOW FRAME is HIGH for an odd field and LOW for an even field. With TXT0.AUTO FRAME HIGH FRAME is only active when text is being displayed, when video is displayed it is forced LOW. When TXT0.DISABLE FRAME is HIGH FRAME is always LOW. If TXT1.FIELD POLARITY is logic 1 then VSYNC is delayed by 32 s before being applied to the display timing circuits.
February 1995
27
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
Clock generator The oscillator circuit of the SAA5290 is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between OSCIN and OSCOUT is basically an inverter biased to the transfer point. A crystal must be used as the feedback element to complete the oscillator
SAA5290
circuitry. It is operated in parallel resonance. OSCIN is the high gain amplifier input and OSCOUT is the output. To drive the SAA5290 externally OSCIN is driven from an external source and OSCOUT is left open-circuit.
handbook, halfpage
handbook, halfpage
OSCGND
not connected
OSCGND
C1
(1)
OSCIN
external clock
OSCIN
C2 (1) OSCOUT
MLC110
not connected
OSCOUT
MLC111
(1) The values of C1 and C2 depend on the crystal specification: C1 = C2 = 2CL.
Fig.7 Oscillator circuit.
Fig.8 Oscillator circuit driven from external source.
February 1995
28
b 0 0 1 1 1 1 0 1 1 B C D E F D E F 7 7a 8 9 A 6 6a 0 0 0 1 1 0 1 1 0 1 1 1 5 0 0 1 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 4 1 0 1 1 1 3 3a 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1
B I T S
7 b
0
0
0
0
0
0
6 b5
0
0
1
handbook, full pagewidth
February 1995
background black back ground red background green background yellow
b
4
0
1
0
b 3 b 2 b1 b 0
CHARACTER SETS
r o w
column
0
1
2
2a
Philips Semiconductors
0
0
0
0
0
alpha numerics black
graphics black
0
0
0
1
1
alpha numerics red
graphics red
0
0
1
0
2
alpha numerics green
graphics green
0
0
1
1
3
alpha numerics yellow
graphics yellow
One page Economy Teletext/TV microcontroller
0
1
0
0
4
alpha numerics blue background blue
graphics blue
0
1
0
1
5
alpha numerics magenta background magenta
graphics magenta
0
1
1
0
6
alpha numerics cyan background cyan
graphics cyan
29
background white normal size OSD double height OSD double width OSD double size OSD
0
1
1
1
7
alpha numerics white
graphics white
1
0
0
0
8
flash
conceal display
1
0
0
1
9
steady
contiguous graphics
1
0
1
0
A
end box
separated graphics
1
0
1
1
B
start box
1
1
0
0
C
normal height
black back ground
1
1
0
1
D
double height
new back ground
1
1
1
0
E
double width
hold graphics
1
1
1
1
F
double size
release graphics
MLC108
Preliminary specification
SAA5290
Fig.9 SAA5290 European character set.
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
SAA5290
handbook, full pagewidth
PHCB LANGUAGE E/W C12 C13 C14 2 / 3 ENGLISH 0 0 0 0 2/4 4/0
CHARACTER POSITION (COLUMN / ROW) 5/B 5/C 5/D 5/E 5/F 6/0 7/B 7/C 7/D 7/E
GERMAN
0
0
0
1
SWEDISH
0
0
1
0
ITALIAN
0
0
1
1
FRENCH
0
1
0
0
SPANISH
0
1
0
1
TURKISH
0
1
1
0
ENGLISH
0
1
1
1
POLISH
1
0
0
0
GERMAN
1
0
0
1
ESTONIAN
1
0
1
0
GERMAN
1
0
1
1
GERMAN
1
1
0
0
SERBO-CROAT
1
1
0
1
CZECHOSLOVAKIA
1
1
1
0
RUMANIAN
1
1
1
1
MLC109
Fig.10 SAA5290 European national option characters.
February 1995
30
40 V EEPROM PCF8582E A0 PH2369 VDD A2 SCL VDD 4.7 k P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P1.7/SDA P2.3/PWM2 P1.6/SCL P1.3/T1 P2.4/PWM3 P2.5/PWM4 P1.2/INT0 P2.6/PWM5 P1.1/T0 P1.0/INT1 V DDM VDD 2.2 F VDD 12 MHz P3.3 OSCIN OSCGND V DDT VDD V DDA VSYNC HSYNC VDS field flyback line flyback VSSD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 100 nF 47 F VDD RESET OSCOUT IR RECEIVER P2.7 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 TV control signals P1.4 P1.5 VSS SDA 47 F 100 nF VDD A1 RC VDD VDD
VDD
Preliminary specification
SAA5290
Fig.11 Typical application diagram.
handbook, full pagewidth
February 1995
Philips Semiconductors
Vtune
VDD
APPLICATION INFORMATION
brightness
contrast
saturation
hue
volume (L)
One page Economy Teletext/TV microcontroller
volume (R)
Vafc
VDD
31
SAA5290
R G B RGBREF P3.4 COR BLACK IREF 27 k V SSD2 FRAME
MLC112
P0.6 P0.7 100 nF 100 nF CVBS1 V SSA CVBS0
VDD
VDD 100 nF 1 k 10 k 3.3 k
to TV's display circuits
1 k
CVBS (IF) CVBS (SCART)
100 nF
seating plane
February 1995
47.92 47.02 4.57 5.08 max max 0.51 min 1.778 (25x) 15.24 1.3 max 17.15 15.90
MSA267
PACKAGE OUTLINE
Philips Semiconductors
handbook, full pagewidth
15.80 15.24
3.2 2.8 0.18 M 0.32 max
One page Economy Teletext/TV microcontroller
1.73 max
0.53 max
32
27 14.1 13.7 26
52
1
Dimensions in mm.
Preliminary specification
SAA5290
Fig.12 Plastic shrink dual in-line package; 52 leads (600 mil) SDIP52, SOT247-1.
Philips Semiconductors
Preliminary specification
One page Economy Teletext/TV microcontroller
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA5290
specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C, it must not be in contact for more than 10 s; if between 300 and 400 C, for not more than 5 s.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
February 1995
33

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